The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a contact silicide in a field effect transistor (FET).
The electrical resistance between a metal contact and source-drain (S-D) region may be reduced by forming a metal silicide atop the S-D region prior to the formation of the metal contact. Typically, the metal silicide may be formed by a self-aligned silicide (salicide) process. In the salicide process, a thin layer of a metal, such as titanium or cobalt, is blanket deposited over a semiconductor substrate, specifically over portions of the S-D region exposed by a contact trench formed in a dielectric layer. The semiconductor substrate may then subjected to one or more annealing steps, which may cause the metal to selectively react with silicon in the exposed portions of the S-D regions to form a metal silicide. The process is referred to as the self-aligned silicide process because the silicide layer is formed only where the metal material directly contacts the exposed portions of the S-D regions.